The present invention relates to calibrating timing of command and data signals on data paths of logic devices, e.g. memory devices, and in particular to using a first data rate slower than the devices"" normal operating rate to transfer a calibration bit pattern between logic devices during calibration.
Memory devices are constantly evolving in the directions of faster speed and higher memory density. To this end, dynamic random access memory (DRAM) devices have evolved from simple DRAM devices to EDO to SDRAM to DDR SDRAM.
One characteristic of modern memory technology is that it may use both the positive- and negative-going edges of a clock cycle to READ and WRITE data to the memory cells and to receive command data from a memory controller. DDR SDRAM represents one example of a modern memory technology that utilizes both positive- and negative-going edges of a clock cycle.
Because of the required high speed operation of contemporary memory devices, system timing and output signal drive level calibration at start-up or reset is a very important aspect of the operation of such devices to compensate for wide variations in individual device parameters or within the system design itself.
One of the several calibration procedures which is performed in current memory devices is a timing synchronization of a clock signal with data provided on an incoming command/address path and on a data path DQ so that incoming data is correctly sampled and outgoing data is correctly timed. Currently, a memory controller achieves this timing calibration at system initialization (start-up or reset) by sending continuous transitions on the clock path and transmitting a 15 bit repeating pseudo random SYNC sequence xe2x80x9c111101011001000xe2x80x9d on the READ/WRITE data path DQ and the command/address path. The memory device determines an optimal internal delay for the clock path relative to arriving command/address and data signals to optimally sample the known bit pattern. This optimal delay is achieved by adjusting the timing of the received data bits to achieve a desired bit alignment relative to the clock. This is accomplished by adjusting a relative timing of clock and data signals, for example setting delay values in the clock or data signal paths, until the received data is properly sampled by the clock and recognized internally. Once synchronization has been achieved, that is, the proper timing on the receiving data or clock paths have been set, the memory controller stops sending the SYNC pattern and the memory device, after all calibrations are completed, can be used for normal memory READ and WRITE access.
To perform the above-described calibration operations, each memory device in a current memory system typically contains means for generating the calibration bit pattern internally, independent of the memory controller. During calibration, the data incoming on a data path under calibration is compared to the internally-generated calibration pattern at each memory device. Internal generation of the calibration bit pattern requires that each memory device contain the additional circuitry needed for pattern generation. For example, each memory device may include the four-bit shift register circuit illustrated in FIG. 6. Because of circuit die size constraints, it would be preferable to simplify the circuitry by avoiding the requirement of generating the calibration bit pattern at every memory device.
While the timing calibration described above, which is conducted at start-up and reset, has been found to perform adequately in most circumstances, there is a problem in that as the data rate of memory devices is increased, the timing margin for data capture is decreased. The timing margin for data capture is the amount of time that valid data is available on the bus or at a device for use during system operations after practical system effects are introduced. For example, for a data transfer rate of 1 GHz (1xc3x97109 Hz), the maximum possible data valid time is only 1 ns (1xc3x9710xe2x88x929 seconds). When practical system effects are introduced, such as accounting for device setup and hold, the timing margin for data capture is even less, for example, a timing margin of less than 100 ps (100xc3x9710xe2x88x9212 seconds) is typical.
This timing margin can be increased by precisely calibrating and aligning the received data with the data capture clock. Improved calibration techniques can reduce the total data arrival time uncertainty that must be accounted for from a theoretical maximum to the actual timing uncertainty observed at the device under actual operating conditions. This reduction in uncertainty results in a corresponding decrease in the timing budget allocated to uncertainty and thus an increase in the timing margin for data capture.
One area in which calibration and alignment with the data capture clock may be improved is in the bit composition of the calibration test pattern. Current systems customarily use a single calibration bit pattern for all calibration operations. Because the same calibration bit pattern may be used for multiple circuit configurations, the bit pattern is designed to test a variety of circuit conditions, although the exact conditions to be encountered are largely unknown at the time of circuit design. The bit pattern may be selected to test a variety of circuit characteristics that affect timing, including static layout length differences, input path delay differences, intersymbol interference, and simultaneously switching outputs.
Moreover, the calibration bit pattern currently in use, for example the 15-bit pseudo random pattern, may not perform optimally for modern high performance memory systems. Because current memory devices capture incoming data on both positive and negative going transitions of the clock signal, even when timing calibration is achieved it may not be clear if alignment was achieved on a positive going or negative going clock edge. That is, the 15-bit synchronization pattern lacks any timing signature. If, for example, synchronization was achieved on the negative going edge of a clock signal when the circuitry is designed on the assumption that synchronization is achieved on a positive going edge, when data is later sampled during memory access the data sampling may be off by one bit. Thus, calibration may be achieved in the wrong phase of the clock signal, leading to incorrect sampling of the data during memory access operations, or requiring additional complicated circuitry to ensure that incoming data is synchronized to the proper phase of the clock.
Therefore, there is a need and desire for an improved calibration technique implementable in logic using simplified circuitry that is capable of compensating for a variety of circuit characteristics that may affect timing.
An improved technique and associated apparatus for timing calibration of a logic device, e.g. a memory device, is provided. A calibration bit pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the bit pattern at the device to be calibrated. Once the pattern is correctly captured and stored, a calibration signal containing the calibration bit s pattern is transmitted to the logic device at the normal operating data rate and timing calibration at the logic device can occur.
The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware. The test bit pattern can thus be adapted to provide a better stimulus for characterizing the timing performance of a particular system or the expected data patterns that the data paths are expected to encounter.
Because the logic for generating the calibration test pattern is no longer required to be included in each system device (i.e., each logic device no longer requires a shift register for generating a local pseudo-random pattern), the invention simplifies the logic and thus reduces die size overhead for many logic devices. The resulting die size savings desirably reduces the cost and complexity of system devices.